SH7615 Datasheet, PDF (545/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Clock
Bus cycle
CPU
CPU
DMAC1 DMAC2 DMAC3 DMAC4
CPU
DREQn
(Active high)
DACKn
(Active high)
RAS
Blind zone
Acceptance
DACK1
DACK2 DACK3 DACK4
CPU
....
CAS
RD/WR
WEn/DQMxx
Figure 11.28 (b) Synchronous DRAM One-Cycle Write Timing
Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory
is set as DRAM and a row address is output during a read or write, the acknowledge signal is
output across the row address and column address (figures 11.29 to 11.31).
Clock
DACKn
(Active high)
Address
bus
Row
Precharge address
Column address
DMAC read or write
(basic timing)
Figure 11.29 DACKn Output in Normal DRAM Accesses (AM = 0 or 1)
Rev. 2.00, 03/05, page 507 of 884