SH7615 Datasheet, PDF (691/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

15.3 Operation
15.3.1 Input
Figure 15.2 shows interval transfer mode (SE set to 1 in SICTR), and figure 15.3 shows
continuous transfer mode (SE cleared to 0 in SICTR).
RDRF
synchronous internal clock
SIRDR
SIRSR
Undefined
SRCK
SRS
SRxD
A[7] A[7:6]
A[7:0]
A[7:1] A[7:0]
A[7] A[6] A[5] A[1] A[0]
Invalid
Note: DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
Figure 15.2 Reception: Interval Transfer Mode
B[7]
B[7]
RDRF
synchronous internal clock
SIRDR
SIRSR
Undefined
SRCK
SRS
SRxD
A[7] A[7:6]
A[7:0]
A[7:1] A[7:0] B[7] B[7:6] B[7:5]
A[7] A[6] A[5]
A[1] A[0] B[7] B[6] B[5]
Note: DL = 0: 8-bit data transfer
SE = 0: Asynchronous transfer, no start signal mode
Figure 15.3 Reception: Continuous Transfer Mode
Rev. 2.00, 03/05, page 653 of 884