SH7615 Datasheet, PDF (143/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Execution of instruction a in B above takes several cycles. If instruction c, which uses the same
resource as instruction a, is issued during execution of instruction a, instruction c is made wait
until the current operation is completed.
Instruction b has no relationship with instruction a and is started without waiting instruction a.
However, its execution may be affected by the control for keeping instruction c in the wait
state and may generate an incorrect result.
If instructions a and c are executed in sequence without instruction b between them, execution
will be completed corrected.
Countermeasures:
This problem is avoided by any of the following countermeasures.
A. Do not execute the instruction sequence shown in B above.
B. Replace instructions b and c above if the program code includes the instruction sequence
shown in B above and replacing instructions b and c does not affect the execution results.
C. Insert one or more NOP instructions or instructions that are not related to the multiplier
between instructions a and b if the program code includes the instruction sequence shown
in B above and replacing instructions b and c does affect the execution results.
Supplementary information:
This usage note is also applicable when a delayed branch instruction comes immediately
before instruction a in B above, the a instruction is placed in the delay slot, and instructions b
and c in B are executed in sequence at the branch destination.
4. This section presents examples of and methods for preventing the instruction execution stall
phenomenon due to multiplier contention caused by multiply and multiply-and-accumulate
instructions.
If the SR (status register) S bit (saturated arithmetic bit) is changed immediately after a
multiply or multiply-and-accumulate instruction in the state where multiplier contention has
occurred due to multiply and/or multiply-and-accumulate instructions and instruction
execution has stalled, the instruction execution order will be reversed. As a result, the
instruction that should have been executed before the S bit was changed will be executed after
the S bit has changed. This can result in an incorrect arithmetic result being produced.
Instructions affected by S bit modification:
Multiply-and-accumulate instructions: MAC.W and MAC.L
Conditions:
The following shows an example of error conditions.
A. Multiply instruction and multiply-and-accumulate instruction
a. DMULU.L R4,R10 MUL.L, DMULS.L, DMULU.L, or MAC.L can be instruction
a.
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