SH7615 Datasheet, PDF (175/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

4.5 Exceptions Triggered by Instructions
4.5.1 Instruction-Triggered Exception Types
Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot
instruction, as shown in table 4.9.
Table 4.9 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Illegal slot
instruction
General illegal
instruction
Source Instruction
Comment
TRAPA
—
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
and instructions that rewrite the
PC
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
Undefined code anywhere
—
besides in a delay slot
4.5.2 Trap Instructions
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The exception service routine start address is fetched from the exception vector table entry that
corresponds to the vector number specified by the TRAPA instruction. That address is jumped
to and the program starts executing. The jump that occurs is not a delayed branch.
Rev. 2.00, 03/05, page 137 of 884