SH7615 Datasheet, PDF (631/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 3—Modem Control Enable (MCE): Enables or disables the CTS and RTS modem control
signals.
Bit 3: MCE
Description
0
Modem signals disabled^*
(Initial value)
1
Modem signals enabled
Note: * CTS is fixed at active-0 regardless of the input value, and RTS output is also fixed at 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit
FIFO data register and resets it to the empty state.
Bit 2: TFRST
Description
0
Reset operation disabled
(Initial value)
1
Reset operation enabled
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST Description
0
Reset operation disabled
(Initial value)
1
Reset operation enabled
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD) and receive
input pin (RxD), enabling loopback testing.
Bit 0: LOOP
0
1
Description
Loopback test disabled
Loopback test enabled
(Initial value)
Rev. 2.00, 03/05, page 593 of 884