SH7615 Datasheet, PDF (393/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

The E-DMAC can perform access involving external memory, but not access involving any on-
chip memory or peripheral modules.
7.10.3 STATS1 and STATS0 Pins
The SH7615 has two pins, STATS1 and STATS0, to identify the bus master status. The signals
output from these pins show the external access status. Encoded output is provided for the
following categories: CPU (cache hit/cache disable), DMAC (external access only), E-DMAC,
and Others (refresh, internal access, etc.). All output is synchronized with the address signals. The
encoding patterns are shown in table 7.9, and the output timing in figure 7.59.
Table 7.9 Encoding Patterns
Identification
CPU
DMAC
E-DMAC
Others
STATS1
0
1
STATS0
0
1
0
1
CKIO
Address
CSn
CPU
CPU E-DMAC E-DMAC E-DMAC E-DMAC G-DMAC G-DMAC G-DMAC
STATS1, 0
00
10
01
Note: In on-chip I/O → on-chip RAM or on-chip I/O → memory transfers using the DMAC,
accesses to on-chip I/O and on-chip RAM are included in the “Others” category.
Figure 7.59 STATS Output Timing
7.10.4 BUSHiZ Specification
The BUSHiZ pin is needed when the SH7615 is connected to a PCI controller via a PCI bridge,
and the PCI master and SH7615 share local memory on the SH7615 bus. By using this pin in
combination with the WAIT pin, it is possible to place the bus and specific control signals in the
high-impedance state while keeping the SH7615's internal state halted. The conditions for
establishing the high-impedance state, the applicable pins, and the bus timing (figure 7.60) are
shown below. See the Application Note for an example of PCI bridge connection.
Rev. 2.00, 03/05, page 355 of 884