SH7615 Datasheet, PDF (510/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 9—Auto Request Mode Bit (AR): Selects either auto-request mode (in which transfer requests
are generated automatically within the DMAC) or a mode using external requests or requests from
on-chip peripheral modules. The AR bit is initialized to 0 by a reset and in standby mode. Its value
is retained during a module standby.
Bit 9: AR
0
1
Description
External/on-chip peripheral module request mode
Auto-request mode
(Initial value)
Bit 8—Acknowledge/Transfer Mode Bit (AM): In dual address mode, this bit selects whether the
DACKn signal is output during the data read cycle or write cycle. In single-address mode, it
selects whether to transfer data from memory to device or from device to memory. The AM bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 8: AM
0
1
Description
DACKn output in read cycle (dual address mode)/transfer from memory
to device (single address mode)
(Initial value)
DACKn output in write cycle (dual address mode)/transfer from device
to memory (single address mode)
Bit 7—Acknowledge Level Bit (AL): Selects whether the DACKn signal is an active-high signal
or an active-low signal. The AL bit is initialized to 0 by a reset and in standby mode. Its value is
retained during a module standby.
Bit 7: AL
0
1
Description
DACKn is an active-low signal
DACKn is an active-high signal
(Initial value)
Bit 6—DREQn Select Bit (DS): Selects the DREQn input detection used. When 0 (level detection)
is set to bit DS, set 0 (cycle-steal mode) to the transfer bus mode bit (TB). When 0 is set to bit DS
and 1 (burst mode) is set to bit TB, system operations are not guaranteed. The DS bit is initialized
to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 6: DS
0
1
Description
Detected by level
Can be set only in cycle-steal mode
Detected by edge
(Initial value)
Rev. 2.00, 03/05, page 472 of 884