SH7615 Datasheet, PDF (843/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 21.7 PLL-On Bus Timing [Modes 0 and 4] (2)
Conditions: V_CC = PLLV_CC = 3.3 V ±5%, PV_CC = 5.0 V ±5%/3.3 V ±5%, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –5 to +70°C, SDRAM bus cycle
Item
Read data setup time 3
(SDRAM)
Read data hold time 4
(SDRAM)
Write data delay time 2
(Iφ:Eφ = 1:1)
Write data hold time 1
Address delay time
CS delay time 1
Read/write delay time
DQM delay time
RAS delay time 1
(SDRAM)
CAS delay time 1
(SDRAM)
CKE delay time
Symbol Min
t_RDS3
6.5
t_RDH4
1.5
t_WDD2
—
t_WDH1
2
t_AD
4
t_CSD1
2.5
t_RWD
2.5
t_DQMD
2.5
t_RASD1
2.5
t_CASD1
2.5
t_CKED
2.5
Max Unit Figure
—
ns 21.16, 17
—
ns 21.16, 17
9.5 ns 21.26, 28
—
ns 21.26, 28
11
ns 21.16, 17, 19, 21, 23, 25, 26, 27,
28, 29, 31, 32, 33
9.5 ns 21.16, 17, 19, 21, 23, 24, 25, 26,
29, 31, 32, 33
9.5 ns 21.16, 17, 19, 21, 22, 23, 25, 26,
29, 30, 31, 32, 33
9.5 ns 21.16, 17, 19, 20, 21, 23, 25, 26,
27, 28, 29, 30
9.5 ns 21.16, 17, 18, 21, 22, 23, 24, 25,
26, 29, 30, 31, 32, 33
9.5 ns 21.16, 17, 18, 19, 23, 24, 25, 26,
27, 28, 29, 31, 32, 33
9.5 ns 21.33
Rev. 2.00, 03/05, page 805 of 884