SH7615 Datasheet, PDF (170/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

4.2.3 Manual Reset
When the NMI pin is low and the RES pin is driven low, the device executes a manual reset. For a
reliable reset, the RES pin should be kept low for at least 20 clock cycles. During a manual reset,
the CPU’s internal state is initialized. All on-chip peripheral module registers are initialized,
except for the bus state controller (BSC), user break controller (UBC), and pin function controller
(PFC) registers, and the frequency modification register (FMR). When the chip enters the manual
reset state in the middle of a bus cycle, manual reset exception handling does not start until the bus
cycle has ended. Thus, manual resets do not abort bus cycles. See appendix B, Pin States, for the
state of individual pins in the manual reset state.
In a manual reset, manual reset exception handling starts when the NMI pin is kept low and the
RES pin is first kept low for a set period of time and then returned to high. The CPU will then
operate in the same way as for a power-on reset.
4.3 Address Errors
4.3.1 Sources of Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 4.6.
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