SH7615 Datasheet, PDF (524/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

DREQ0
DREQ1
Bus
cycle
CPU
CPU
Channel 0
source
Channel 1
source
Channel 0
source
CPU
CPU
CPU
Channel 0
destination
Channel 1
destination
Figure 11.4 Fixed Mode DMA Transfer in Cycle-Steal Mode
(Dual Address, DREQn Low-Level Detection)
Round-Robin Mode: Switches the priority of channel 0 and channel 1, shifting their ability to
receive transfer requests. Each time one transfer ends on one channel, the priority shifts to the
other channel. The channel on which the transfer just finished is assigned low priority. After reset,
channel 1 has higher priority than channel 0.
Figure 11.5 shows how the priority changes when channel 0 and channel 1 transfers are requested
simultaneously and another channel 0 transfer is requested after the first two transfers end. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 1 and 0.
2. Channel 1 has the higher priority, so the channel 1 transfer begins first (channel 0 waits for
transfer).
3. When the channel 1 transfer ends, channel 1 becomes the lower-priority channel.
4. The channel 0 transfer begins.
5. When the channel 0 transfer ends, channel 0 becomes the lower-priority channel.
6. A channel 0 transfer is requested.
7. The channel 0 transfer begins.
8. When the channel 0 transfer ends, channel 0 is already the lower-priority channel, so the order
remains the same.
Rev. 2.00, 03/05, page 486 of 884