SH7615 Datasheet, PDF (255/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

BDRC Configuration
XYEC = 0
XYEC = 1
Data
X data
(when XYSC = 0)
Y data
(when XYSC = 1)
Upper 16 Bits
(BDC31 to BDC16)
Upper 16 bits of data bus
X data
(XDB15 to XDB0)
—
Lower 16 Bits
(BDC15 to BDC0)
Lower 16 bits of data bus
—
Y data
(YDB15 to YDB0)
6.2.10 Break Data Mask Register C (BDMRC)
BDMRCH
Bit: 15
14
13
12
11
10
9
8
BDMC31 BDMC30 BDMC29 BDMC28 BDMC27 BDMC26 BDMC25 BDMC24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BDMC23 BDMC22 BDMC21 BDMC20 BDMC19 BDMC18 BDMC17 BDMC16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BDMRCL
Bit: 15
14
13
12
11
10
9
8
BDMC15 BDMC14 BDMC13 BDMC12 BDMC11 BDMC10 BDMC9 BDMC8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BDMC7 BDMC6 BDMC5 BDMC4 BDMC3 BDMC2 BDMC1 BDMC0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Break data mask register C (BDMRC) consists of two 16-bit readable/writable registers: break
data mask register CH (BDMRCH) and break data mask register CL (BDMRCL). BDMRCH
specifies which bits of the break data set in BDRCH are to be masked, and BDMRCL specifies
which bits of the break data set in BDRCL are to be masked. Operation also depends on bits
XYEC and XYSC in BBRC as shown below. BDMRCH and BDMRCL are initialized to H'0000
by a power-on reset; after a manual reset, their values are undefined.
Rev. 2.00, 03/05, page 217 of 884