SH7615 Datasheet, PDF (240/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.1.2 Block Diagram
Address
Access
Channel A
Address
Access
Channel B
BARAH BARAL
BAMRAH BAMRAL
BBRA
BARBH BARBL
BAMRBH BAMRBL
BBRB
Address
Data
Access
Channel C
BARCH BARCL
BAMRCH BAMRCL
BDRCH BDRCL
BDMRCH BDMRCL
BBRC
BETRC
Address
BARDH BARDL
BAMRDH BAMRDL
Data
Access
Channel D
BDRDH BDRDL
BDMRDH BDMRDL
BBRD
BETRD
PC trace
Control
BRSRH BRSRL
BRDRH BRDRL
BRFR
BRCRH BRCRL
Internal interrupt signal
BARAH/L: Break address register AH/L
BAMRAH/L: Break address mask register AH/L
BBRA:
Break bus cycle register A
BARBH/L: Break address register BH/L
BAMRBH/L: Break address mask register BH/L
BBRB:
Break bus cycle register B
BARCH/L: Break address register CH/L
BAMRCH/L: Break address mask register CH/L
BDRCH/L: Break data register CH/L
BDMRCH/L: Break data mask register CH/L
BBRC:
Break bus cycle register C
BETRC:
Break execution times register C
BARDH/L: Break address register DH/L
BAMRDH/L: Break address mask register DH/L
BDRDH/L: Break data register DH/L
BDMRDH/L: Break data mask register DH/L
BBRD:
Break bus cycle register D
BETRD:
Break execution times register D
BRCRH/L: Break control register H/L
BRFR:
Branch flag register
BRSRH/L: Branch source register H/L
BRDRH/L: Branch destination register H/L
Figure 6.1 Block Diagram of User Break Controller
Rev. 2.00, 03/05, page 202 of 884