SH7615 Datasheet, PDF (483/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 0—Reserved: This bit is always read as 0. The write value should always be 0.
10.2.14 Receiving-Buffer Write Address Register (RBWAR)
This is the register for storing the buffer address to be written in the receiving buffer when the E-
DMAC writes data in the receiving buffer. Which addresses in the receiving buffer are processed
by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Bit: 31
30
29
28
27
26
25
24
RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA9 RBWA8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
RBWA7 RBWA6 RBWA5 RBWA4 RBWA3 RBWA2 RBWA1 RBWA0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 31 to 0—Receiving-buffer write address (RBWA): This bit can only be read. Writing is
disabled.
Note: The buffer write processing result from the E-DMAC and the value read by the register
may not be the same.
Rev. 2.00, 03/05, page 445 of 884