SH7615 Datasheet, PDF (529/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

This LSI
DMAC
External data bus
2
External
memory
External
memory
1
: Data flow
1: Read cycle
2: Write cycle
Figure 11.8 Data Flow in Dual Address Mode
In dual address mode transfers, external memory and memory-mapped external devices can be
mixed without restriction. Specifically, this enables transfers between the following:
 Transfer between external memory and external memory
 Transfer between external memory and memory-mapped external device
 Transfer between memory-mapped external device and memory-mapped external device
 Transfer between external memory and on-chip peripheral module (excluding DMAC,
BSC, UBC, cache, E-DMAC, and EtherC)*
 Transfer between memory-mapped external device and on-chip peripheral module
(excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)*
 Transfer between on-chip memory and on-chip memory
 Transfer between on-chip memory and memory-mapped external device
 Transfer between on-chip memory and on-chip peripheral module (excluding DMAC,
BSC, UBC, cache, E-DMAC, and EtherC)*
 Transfer between on-chip memory and external memory
 Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-
DMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache,
E-DMAC, and EtherC)*
Note: * Access size permitted by peripheral module register used as transfer source or
transfer destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC).
Rev. 2.00, 03/05, page 491 of 884