SH7615 Datasheet, PDF (122/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 2.24 Branch Instructions
Instruction
Instruction Code Operation
Cycles
BF
label 10001011dddddddd If T = 0, disp × 2 + PC → PC,
3/1^*
if T = 1, nop
BF/S label 10001111dddddddd Delayed branch, if T = 0,
2/1^*
disp × 2 + PC → PC, if T = 1, nop
BT
label 10001001dddddddd If T = 1, disp × 2 + PC → PC,
3/1^*
if T = 0, nop
BT/S label 10001101dddddddd Delayed branch,
2/1^*
if T = 1, disp × 2 + PC → PC,
if T = 0, nop
BRA label 1010dddddddddddd Delayed branch,
2
disp × 2 + PC → PC
BRAF Rm
0000mmmm00100011 Delayed branch, Rm + PC → PC 2
BSR label 1011dddddddddddd Delayed branch, PC → PR,
2
disp × 2 + PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch,
2
PC → PR, Rm + PC → PC
JMP @Rm
0100mmmm00101011 Delayed branch, Rm → PC
2
JSR @Rm
0100mmmm00001011 Delayed branch,
2
PC → PR, Rm → PC
RTS
0000000000001011 Delayed branch, PR → PC
2
Note: * One state when it does not branch.
T Bit
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Rev. 2.00, 03/05, page 84 of 884