SH7615 Datasheet, PDF (886/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

21.3.8 Serial I/O Timing
Table 21.13 Serial I/O Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
SRCK, STCK clock input cycle time
Symbol
t_sIcyc
SRCK, STCK clock input low-level width
SRCK, STCK clock input high-level width
SRS input setup time
SRS input hold time
SRXD input setup time
SRXD input hold time
STS input setup time
STS input hold time
STS output delay time
STXD output delay time
t_{W L}
t_WH
t_RSS
t_RSH
t_SRDS
t_SRDH
t_TSS
t_TSH
t_TSD
t_TDD
Min
t_Pcyc or^*
66.7
0.4 × t_sIcyc
0.4 × t_sIcyc
15
10
15
10
15
10
0
0
Max
—
—
—
—
—
—
—
—
—
20
20
Note: * Specified as tPcyc or 66.7, whichever is greater.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
21.61
21.62
21.63
21.64
21.63,
21.64
STCKn, SRCKn
t_sIcyc
t_WL
t_WH
n = 0, 1, or 2
Figure 21.61 SIO Input Clock Timing
Rev. 2.00, 03/05, page 848 of 884