SH7615 Datasheet, PDF (45/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Direct memory
access controller
(DMAC),
2 channels
On-chip RAM
Ethernet controller
direct memory
access controller
(E-DMAC),
2 channels
Specifications
• 4-Gbyte address space, maximum 16M (16,777,216) transfers
• Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length
• Parallel execution of CPU instruction processing and DMA operation
possible in case of cache hit
• Selection of dual address or single address mode
 Single address (data transfer rate of one transfer unit in one bus cycle)
 Dual address (data transfer rate of one transfer unit in two bus cycles)
 When synchronous DRAM is connected, 16-byte continuous read →
continuous write transfer is available (dual)
 When synchronous DRAM is connected, single-address transfer is
available in a single clock cycle at maximum 31.25 MHz
• Cycle stealing or burst transfer
• Relative channel priorities can be set (fixed mode/round robin mode)
• DMA transfer is possible for the following devices:
 External memory, on-chip memory, on-chip supporting modules
(excluding DMAC, BSC, UBC, cache, E-DMAC, EtherC)
• External requests, DMA transfer requests from on-chip supporting
modules, auto requests
• Interrupt request (DEIn) can be issued to CPU at end of data transfer
• DACK used for DREQ sampling (however, there is always one overrun as
there is one acceptance before first DACK)
• 4-kbyte X-RAM
• 4-kbyte Y-RAM
• Transfer possible between EtherC and external memory/on-chip memory
• 16-byte burst transfer possible
• Single address transfer
• Chain block transfer
• 32-bit transfer data width
• 4-Gbyte address space
Rev. 2.00, 03/05, page 7 of 884