SH7615 Datasheet, PDF (613/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE
Description
0
Reception disabled^*1
1
Reception enabled^*2
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDF, DR, FER, PER, ORER, ER, and BRK
flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SCSMR settings must be made to decide the reception format before setting the RE bit
to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1.
The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1
Multiprocessor interrupts enabled^*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and
setting of the RDF and FER in SC1SSR and ORER in SC2SSR are disabled
until data with the multiprocessor bit set to 1 is received.
Note: * Receive data transfer from SCRSR to SCFRDR, receive error detection, and setting of
the RDF and FER in SC1SSR and ORER flags in SC2SSR, is not performed. When
receive data with MPB = 1 is received, the MPB flag in SC2SSR is set to 1, the MPIE bit
is cleared to 0 automatically, and generation of RXI and ERI (when the RIE bit in
SCSCR is set to 1) and FER and ORER flag setting is enabled.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 575 of 884