SH7615 Datasheet, PDF (458/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 10.1 E-DMAC Registers
Name
Abbre-
viation
E-DMAC mode register
EDMR
E-DMAC transmit request register
EDTRR
E-DMAC receive request register
EDRRR
Transmit descriptor list address register TDLAR
Receive descriptor list address register
RDLAR
EtherC/E-DMAC status register
EESR
EtherC/E-DMAC status interrupt
permission register
EESIPR
Transmit/receive status copy enable
register
TRSCER
Receive missed-frame counter register
RMFCR
Transmit FIFO threshold register
TFTR
FIFO depth register
FDR
Receiver control register
RCR
E-DMAC operation control register
EDOCR
Receive buffer write address register
RBWAR
Receive descriptor fetch address register RDFAR
Transmit buffer read address register
TBRAR
Transmit descriptor fetch address register TDFAR
Notes: 1. Individual bits are cleared by writing 1.
2. Cleared by reading the register.
R/W
R/W
R/W
R/W
R/W
R/W
R/W^*1
R/W
R/W
R/W^*2
R/W
R/W
R/W
R/W
R
R
R
R
Initial Value
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
Address
H'FFFFFD00
H'FFFFFD04
H'FFFFFD08
H'FFFFFD0C
H'FFFFFD10
H'FFFFFD14
H'FFFFFD18
H'FFFFFD1C
H'FFFFFD20
H'FFFFFD24
H'FFFFFD28
H'FFFFFD2C
H'FFFFFD30
H'FFFFFD40
H'FFFFFD44
H'FFFFFD4C
H'FFFFFD50
Rev. 2.00, 03/05, page 420 of 884