SH7615 Datasheet, PDF (387/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

8-bit data width memory. Bus arbitration is performed between external vector fetch, PC save, and
SR save cycles during interrupt handling, which are all independent accesses.
Because the CPU is connected to cache memory by a dedicated internal bus, cache memory can be
read even when the bus is being used by another bus master on the chip or externally. When
writing from the CPU, an external write cycle is produced. Since the internal bus that connects the
CPU, DMAC, and on-chip peripheral modules can operate in parallel to the external bus, both read
and write accesses from the CPU to on-chip peripheral modules and from the DMAC to on-chip
peripheral modules are possible even if the external bus is not held.
Figures 7.57 (a) and 7.57 (b) show the timing charts in the cases that bus requests occur
simultaneously from the E-DMAC, DMAC, and CPU. These cases are based on the following
settings:
• The CS2 and CS3 spaces are set for synchronous DRAM.
• The CAS latency is one cycle.
• The E-DMAC is enabled at both the transmitter and receiver (the buffer and descriptor use the
CS3 space).
• The DMAC is enabled in only one channel that is set to auto-request mode, cycle-steal mode,
and 16-byte dual-address transmission (CS2 space).
• Burst read and single write are set to synchronous DRAM.
Rev. 2.00, 03/05, page 349 of 884