SH7615 Datasheet, PDF (708/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be
modified.
Bit 4: BFA
0
1
Description
TGRA operates normally
TGRA and TGRC used together for buffer operation
(Initial value)
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3: Bit 2: Bit 1:
MD3^*1 MD2^*2 MD1
Bit 0:
MD0
Description
0
0
0
0
Normal operation
(Initial value)
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
1
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
1
*
*
*
—
*: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to MD2.
Rev. 2.00, 03/05, page 670 of 884