SH7615 Datasheet, PDF (286/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

DMA Data Access Cycle Break Condition Settings
Register settings: BARA = H'00314156 / BAMRA = H'00000000 / BBRA = H'0094
BBRB = H'0000
BBRC = H'0000
BARD = H'00055555 / BAMRD = H'00000000 / BBRD = H'00A9
BDRD = H'00007878 / BDMRD = H'00000F0F
BRCR = H'00000008
Set conditions: All channels independent
Channel A: Address: H'00314156; address mask: H'00000000
Bus cycle: DMAC, instruction fetch, read (operand not
included in conditions)
Channel B: Not used
Channel C: Not used
Channel D: Address: H'00055555; address mask: H'00000000
Data:
H'00007878; data mask: H'00000F0F
Bus cycle: DMAC, data access, write, byte
On channel A, a user break interrupt is not generated as an instruction fetch is not performed in
a DMAC cycle.
On channel D, a user break interrupt is generated when the DMAC writes H'7* (*: Don't care)
is written by byte access to address H'00055555.
Rev. 2.00, 03/05, page 248 of 884