SH7615 Datasheet, PDF (345/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.5.7 Bank Active Function
A synchronous DRAM bank function is used to support high-speed accesses of the same row
address. When the RASD bit in MCR is set to 1, read/write accesses are performed using
commands without auto-precharge (READ, WRIT). In this case, even when the access is
completed, no precharge is performed. This function is not supported in the CS2 space. When the
bank active function is used, no precharge is performed when the access is completed. When
accessing the same row address in the same bank, a READ or WRIT command can be called
immediately without calling an ACTV command, just like the RAS down mode of the DRAM’s
high-speed page mode. Synchronous DRAM is divided into two banks, so one row address in each
can stay active. When the next access is to a different row address, a PRE command is called first
to precharge the bank, and access is performed by an ACTV command and READ or WRIT
command in order, after the precharge is completed. With successive accesses to different row
addresses, the precharge is performed after the access request occurs, so the access time is longer.
When writing, performing an auto-precharge means that no command can be called for tRWL +
tAP cycles after a WRITA command is called. When the bank active mode is used, READ or
WRIT commands can be issued consecutively if the row address is the same. This shortens the
number of cycles by tRWL + tAP for each write. The number of cycles between the issue of the
precharge command and the row address strobe command is determined by the TRP1, TRP0 in
MCR.
Whether execution is faster when the bank active mode is used or when basic access is used is
determined by the proportion of accesses to the same row address (P1) and the average number of
cycles from the end of one access to the next access (tA). When tA is longer than tAP, the delay
waiting for the precharge during a read becomes invisible. If tA is longer than tRWL + tAP, the
delay waiting for the precharge also becomes invisible during writes. The difference between the
bank active mode and basic access speeds in these cases is the number of cycles between the start
of access and the issue of the read/write command: (tRP + tRCD) × (1 – P1) and tRCD,
respectively.
The time that a bank can be kept active, tRAS, is limited. When the period will be provided by
program execution, and it is not assured that another row address will be accessed without a hit to
the cache, the synchronous DRAM must be set to auto-refresh and the refresh cycle must be set to
the maximum value tRAS or less. This enables the limit on the maximum active period for each
bank to be ensured. When auto-refresh is not being used, some measure must be taken in the
program to ensure that the bank does not stay active for longer than the prescribed period.
Figure 7.24 (a) and (b) show burst read cycles that is not an auto-precharge cycle, figure 7.25 (a)
and (b) show burst read cycles to a same row address, figure 7.26 (a) and (b) show burst read
cycles to different row addresses, figure 7.27 shows a write cycle without auto-precharge, figure
7.28 shows a write cycle to a same row address, and figure 7.29 shows a write cycle to different
row addresses.
Rev. 2.00, 03/05, page 307 of 884