SH7615 Datasheet, PDF (235/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Write completed
Next interrupt can be accepted
Interrupt clear instruction D E M
Synchronization instruction
DEM
RTE instruction
D
External write
cycle
External read
W _cycle
E MM
Delay slot instruction
Interrupt return destination instruction
DE
F DE
0.5Icyc + 1.0Ecyc + 1.5Pcyc
IRL3–IRL0
F: Instruction fetch ............... Instruction is fetched from memory in which program is stored
D: Instruction decode ........... Fetched instruction is decoded
E: Instruction execution ........ Data operation or address operation is performed in accordance
with result of decoding
M: Memory access ................ Memory data access is performed
W: Write-back ....................... Data read from memory is written to register
Figure 5.11 Pipeline Operation when Returning by Means of RTE Instruction
Write completed
Next interrupt can be accepted
Interrupt clear instruction D E M
Synchronization instruction
•
•
•
LDC instruction
DEM
External write
cycle
External read
W _cycle
DE
Interrupt disable instruction
DE
Normal instruction
DE
0.5Icyc + 1.0Ecyc + 1.5Pcyc
IRL3–IRL0
Figure 5.12 Pipeline Operation when Interrupts are Enabled by Means of SR Modification
When an interrupt source is cleared by the program, pipeline operation must be considered
to ensure that the same interrupt is not implemented again.
Rev. 2.00, 03/05, page 197 of 884