SH7615 Datasheet, PDF (768/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.8 Usage Notes
16.8.1 Clearing Flags in TSR0 to TSR2
When bits TCFV, TGFD, TGFC, TGFB, and TGFA in TSR0, and bits TCFU, TCFV, TGFB, and
TGFA in TSR1 and TSR2, are cleared, it may happen that the interrupt request in the internal
logic cannot be cleared although the flag is cleared. In this case, if interrupt acceptance is enabled,
another interrupt will be generated.
Either of the following measures should therefore be taken when clearing flags in TSR0 to TSR2.
1. Execute clearing while the TPU timer is counting up.
2. If clearing when the TPU timer is stopped, write 0 to the flag again after executing clearing.
16.8.2 DMA Transfer by TPU0
When DMA transfer is performed by means of TPU channel 0 compare match or input capture,
internal logic interrupt requests (transfer requests) may not be cleared correctly. Therefore, it may
not be possible to execute DMA transfer when a subsequent transfer request is generated by TPU
channel 0 compare match or input capture.
Either of the following measures should therefore be taken when performing DMA transfer by
means of TPU channel 0 compare match or input capture.
1. Do not set on-chip RAM as the DMA transfer source or destination.
2. When on-chip RAM has not been set as the DMA transfer source or destination, execute the
transfer while the TPU channel 0 timer is counting up.
Rev. 2.00, 03/05, page 730 of 884