SH7615 Datasheet, PDF (418/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.1.3 Input/Output Pins
The EtherC has signal pins compatible with the 18-pin MII specified in the IEEE802.3u standard,
and three related signal pins to simplify connection to the PHY-LSI. The pin configuration are
shown in table 9.1.
Table 9.1 Pin Configuration
Type
MII
Other
Abbre-
viation
TX-CLK
Name
Transmit clock
I/O
Input
RX-CLK Receive clock
Input
TX-EN Transmit enable
Output
ETXD0 to
ETXD3
TX-ER
RX-DV
Transmit data (4-bit) Output
Transmit error
Receive data valid
Output
Input
ERXD0 to
ERXD3
RX-ER
Receive data (4-bit)
Receive error
Input
Input
CRS
COL
MDC
MDIO
Carrier detect
Collision detect
Management data
clock
Management data
input/output
Input
Input
Output
Input/
output
LNKSTA
EXOUT
WOL
Link status
General-purpose
external output
Wake-On-LAN
Input
Output
Output
Function
TX-EN, ETXD0 to ETXD3, TX-ER timing
reference signal
RX-DV, ERXD0 to ERXD3, RX-ER timing
reference signal
Indicates that transmit data is ready on
ETXD0 to ETXD3
4-bit transmit data
Notifies PHY-LSI of error during transmission
Indicates that there is valid receive data on
ERXD0 to ERXD3
4-bit receive data
Identifies error state occurring during data
reception
Carrier detection signal
Collision detection signal
Reference clock signal for information
transfer via MDIO
Bidirectional signal for exchange of
management information between STA and
PHY
Inputs link status from PHY-LSI
External output pin
Magic packet reception
Rev. 2.00, 03/05, page 380 of 884