SH7615 Datasheet, PDF (812/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

19.2.1 Register Configuration
The port A register is shown in table 19.1.
Table 19.1 Register Configuration
Name
Port A data register
Abbreviation R/W
PADR
R/W
Initial Value
H'0000
Address
Access Size
H'FFFFFC84 8, 16
19.2.2 Port A Data Register (PADR)
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
— PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PA7DR PA6DR PA5DR PA4DR — PA2DR PA1DR PA0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
R
R/W R/W R/W
The port A data register (PADR) is a 16-bit read/write register that stores port A data. Bits 15, 14,
and 3 are reserved: they always read 0, and the write value should always be 0. Bits PA13DR to
PA0DR correspond to pins PA13 to PA0. When a pin functions as a general output, if a value is
written to PADR, that value is output directly from the pin, and if PADR is read, the register value
is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is
read the pin state, not the register value, is returned directly. If a value is written to PADR,
although that value is written into PADR it does not affect the pin state. Table 19.2 summarizes
port A data register read/write operations.
PADR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in
standby mode or sleep mode.
Rev. 2.00, 03/05, page 774 of 884