SH7615 Datasheet, PDF (676/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Base clock
Receive data
(RxD)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
–7.5 clocks
+7.5 clocks
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.25 Receive Data Sampling Timing in Asynchronous Mode
(Using base clock with frequency of 16 times the transfer rate, sampled in 8th clock cycle)
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
................. ............ (1)
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16, 8, or 4)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5, F = 0, and N = 16:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%...................................................................................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
When Using Synchronous External Clock Mode
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
SCK has changed from 0 to 1.
• Only set both TE and RE to 1 when external clock SCK is 1.
• In reception, note that if RE is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles
after the rising edge of the RxD D7 bit SCK input, RDF will be set to 1 but copying to
SCFRDR will not be possible.
Rev. 2.00, 03/05, page 638 of 884