SH7615 Datasheet, PDF (33/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

11.2.6 DMA Request/Response Selection Control Registers 0 and 1
(DRCR0, DRCR1)............................................................................................... 475
11.2.7 DMA Operation Register (DMAOR) .................................................................. 477
11.3 Operation .......................................................................................................................... 479
11.3.1 DMA Transfer Flow ............................................................................................ 479
11.3.2 DMA Transfer Requests ...................................................................................... 481
11.3.3 Channel Priorities ................................................................................................ 485
11.3.4 DMA Transfer Types........................................................................................... 488
11.3.5 Number of Bus Cycles......................................................................................... 498
11.3.6 DMA Transfer Request Acknowledge Signal Output Timing............................. 498
11.3.7 DREQn Pin Input Detection Timing.................................................................... 509
11.3.8 DMA Transfer End .............................................................................................. 515
11.3.9 BH Pin Output Timing......................................................................................... 516
11.4 Usage Examples................................................................................................................ 517
11.4.1 Example of DMA Data Transfer Between On-chip SCIF and External Memory 517
11.5 Usage Notes ...................................................................................................................... 518
Section 12 16-Bit Free-Running Timer (FRT) ........................................................... 525
12.1 Overview........................................................................................................................... 525
12.1.1 Features................................................................................................................ 525
12.1.2 Block Diagram..................................................................................................... 526
12.1.3 Input/Output Pins................................................................................................. 527
12.1.4 Register Configuration......................................................................................... 527
12.2 Register Descriptions........................................................................................................ 528
12.2.1 Free-Running Counter (FRC) .............................................................................. 528
12.2.2 Output Compare Registers A and B (OCRA and OCRB) ................................... 528
12.2.3 Input Capture Register (FICR) ............................................................................ 529
12.2.4 Timer Interrupt Enable Register (TIER).............................................................. 529
12.2.5 Free-Running Timer Control/Status Register (FTCSR) ...................................... 530
12.2.6 Timer Control Register (TCR)............................................................................. 532
12.2.7 Timer Output Compare Control Register (TOCR) .............................................. 533
12.3 CPU Interface ................................................................................................................... 534
12.4 Operation .......................................................................................................................... 537
12.4.1 FRC Count Timing .............................................................................................. 537
12.4.2 Output Timing for Output Compare .................................................................... 538
12.4.3 FRC Clear Timing ............................................................................................... 538
12.4.4 Input Capture Input Timing ................................................................................. 539
12.4.5 Input Capture Flag (ICF) Setting Timing ............................................................ 540
12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing ....................................... 540
12.4.7 Timer Overflow Flag (OVF) Setting Timing....................................................... 541
12.5 Interrupt Sources............................................................................................................... 542
12.6 Example of FRT Use ........................................................................................................ 542
12.7 Usage Notes ...................................................................................................................... 543
Rev. 2.00, 03/05, page xxxiii of xxxviii