SH7615 Datasheet, PDF (516/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 2: AE
0
1
Description
No DMAC address error
To clear the AE bit, read 1 from it and then write 0
Address error by DMAC
(Initial value)
Bit 1—NMI Flag Bit (NMIF): This flag indicates that an NMI interrupt has occurred. When the
NMIF bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel
control register (CHCR) and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and
then write 0. Operation is completed up to the end of the DMAC transfer being executed when
NMI was input. When the NMI interrupt is input while the DMAC is not operating, the NMIF bit
is set to 1. The NMIF bit is initialized to 0 by a reset or in the standby mode. It retains its value
when the module standby function is used.
Bit 1: NMIF
0
1
Description
No NMIF interrupt
To clear the NMIF bit, read 1 from it and then write 0
NMIF interrupt has occurred
(Initial value)
Bit 0—DMA Master Enable Bit (DME): Enables or disables DMA transfers on all channels. A
DMA transfer becomes enabled when the DE bit in the CHCR and the DME bit are set to 1. For
this to be effective, the TE bit in CHCR and the NMIF and AE bits must all be 0. When the DME
bit is cleared, all channel DMA transfers are aborted. DME is initialized to 0 by a reset and in
standby mode. It retains its value when the module standby function is used.
Bit 0: DME
0
1
Description
DMA transfers disabled on all channels
DMA transfers enabled on all channels
(Initial value)
Rev. 2.00, 03/05, page 478 of 884