SH7615 Datasheet, PDF (321/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

CKIO
A24–A0
CSn
RD/WR
Read
RD
D31–D0
Write
WEn
D31–D0
BS
DACKn*
T₁
T₂
Note: * DACKn waveform when active-low is specified.
Figure 7.8 Basic Timing of Ordinary Space Access
When making a word or longword access with an 8-bit bus width, or a longword access with a 16-
bit bus width, the bus state controller performs multiple accesses.
When clock ratio except Iφ:Eφ = 1:1, the basic timing shown in figure 7.8 is repeated, but when
clock ratio Iφ:Eφ is 1:1, burst access with no CSn negate period is performed as shown in figure
7.9.
Rev. 2.00, 03/05, page 283 of 884