SH7615 Datasheet, PDF (638/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

14.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure,
so that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 14.3 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCIF monitors the line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (LSB-first
or MSB-first order selectable), a parity bit or multiprocessor bit (high or low level), and finally
one or two stop bits (high level).
In asynchronous mode, the SCIF performs synchronization at the falling edge of the start bit in
reception. The SCIF samples the data on the eighth (fourth, second) pulse of a clock with a
frequency of 16 (8, 4) times the length of one bit, so that the transfer data is latched at the center of
each bit.
1
Serial
data
(LSB)
0
D0 D1
Start
bit
1 bit
D2 D3 D4 D5
Transmit/receive data
7 or 8 bits
(MSB)
Idle state (mark state)
1
D6 D7 0/1 1
1
Parity Stop
bit
bit(s)
1 bit, 1 or
or none 2 bits
One unit of transfer data (character or frame)
Figure 14.3 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits, LSB-First Transfer)
Rev. 2.00, 03/05, page 600 of 884