SH7615 Datasheet, PDF (776/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

17.3.3 Data Register (SDDR)
The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each
of which has the following configuration.
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is
connected to TDO and TDI for serial data transfer to and from an external device.
32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the
last 32 bits will be stored in SDDR. Serial data is input starting from the MSB of SDDR (bit 15 of
SDDRH), and output starting from the LSB (bit 0 of SDDRL).
This register is not initialized by a reset, in standby mode, or by the TRST signal.
17.3.4 Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit shift register. In bypass mode, CLAMP mode, and
HIGHZ mode, SDBPR is connected to TDI and TDO, and the chip is excluded from the board test
when a boundary scan test is conducted. SDBPR cannot be read or written to by the CPU.
17.3.5 Boundary Scan Register (SDBSR)
The boundary scan register (SDBSR), a shift register that controls the I/O terminals of this LSI, is
provided on the PAD.
Using the EXTEST mode or the SAMPLE/PRELOAD mode, a boundary scan test conforming to
the IEEE1149.1 standard can be performed.
For SDBSR, read/write by the CPU cannot be performed.
Table 17.5 shows the relationship between the terminals of the LSI and the boundary scan register.
Rev. 2.00, 03/05, page 738 of 884