SH7615 Datasheet, PDF (371/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

An address comparator is provided to detect matches of row addresses in burst mode. When this
function is used and the BE bit in MCR is set to 1, setting the MCR’s RASD bit (which specifies
RAS down mode) to 1 places the SH7615 in RAS down mode, which leaves the RAS signal
asserted. The access timing in RAS down mode is shown in figures 7.44 and 7.45. When RAS
down mode is used, the refresh cycle must be less than the maximum DRAM RAS assert time
tRAS when the refresh cycle is longer than the tRAS maximum.
Tp
CKIO
A24–A16
A15–A1
RAS
CASn
RD/WR
Read RD
D31–D0
RD/WR
Write _RD
D31–D0
DACKn*
Tr
Tc1
Tc2
Tc1
Tc2
Note: * DACKn waveform when active-low is specified
Figure 7.43 Burst Access Timing
Rev. 2.00, 03/05, page 333 of 884