SH7615 Datasheet, PDF (550/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• Cycle-Steal Mode Edge Detection—16-Bit Transfer
With 16-byte transfer, the first request signal is the first transfer request, and the second
transfer request is accepted when the next request signal is accepted. The third and fourth
requests are accepted in the same way.
Transfer Width
Transfer bus mode
Transfer address mode
16-Byte Transfer
Cycle-steal mode
Dual/single mode
DREQn Detection
Method
DACKn output timing
Bus cycle
Edge Detection
Read DACK/write
DACK
Basic bus cycle
Clock
Bus cycle
CPU CPU ^{DMAC*1 DMAC*2 DMAC*3 DMAC*4 DMA}
DREQn
(Active high)
DACKn
(Active high)
Blind zone
1st
2nd
acceptance acceptance
DACK*1 DACK*2 DACK*3 DACK*4
Note: * n is the nth 16-byte transfer.
Figure 11.37 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection
(16-Byte Transfer Setting)
Rev. 2.00, 03/05, page 512 of 884