SH7615 Datasheet, PDF (688/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 4—Transmit/Receive Data Length Select (DL): Specifies the serial I/O module’s transfer data
length. The initial value of this bit is 0, indicating an 8-bit data length. When an 8-bit data length
is specified, the lower 8 bits of each I/O register are used.
Bit 4: DL
0
1
Description
8-bit transfer data length
16-bit transfer data length
(Initial value)
Bit 3—Transmit Interrupt Enable (TIE): Enables the transmit-data-empty interrupt. The initial
value of this bit is 0.
Bit 3: TIE
0
1
Description
Transmit interrupt disabled
Transmit interrupt enabled
(Initial value)
Bit 2—Receive Interrupt Enable (RIE): Enables the receive-data-full interrupt. The initial value of
this bit is 0.
Bit 2: RIE
0
1
Description
Receive interrupt disabled
Receive interrupt enabled
(Initial value)
Bit 1—Transmit Enable (TE): Enables data transmission. When this flag is cleared, the STxD,
STCK, and STS pins go to the high-impedance state.
Bit 1: TE
0
1
Description
Transmission disabled: STxD, STCK, and STS pins go to high-impedance
state
(Initial value)
Transmission enabled
Bit 0—Receive Enable (RE): Enables data reception. When this flag is cleared, the SRxD, SRCK,
and SRS pins go to the high-impedance state.
Bit 0: RE
0
1
Description
Reception disabled: SRxD, SRCK, and SRS pins go to high-impedance state
(Initial value)
Reception enabled
Rev. 2.00, 03/05, page 650 of 884