SH7615 Datasheet, PDF (159/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

; PLL circuits 1 and 2 → Enabled.
; Iφ (×4) = 62.5 MHz, Eφ (×1) = 15.625 MHz,
; Pφ (×1) = 15.625 MHz, CKIO (Eφ) = 15.625 MHz,
; MOV #H'08,R0
MOV.B R0,@R4
rts
nop
FREQUENCY_END:
NOP
.END
Cautions
• The read from the external memory space 0–4 cache-through area and the write to the
frequency modification register should be performed in on-chip X/Y memory. After reading
from the external memory space 0–4 cache-through area, do not perform any write operations
in external memory spaces 0–4 until the write to the frequency modification register.
• When the write access to the frequency modification register is executed, the WDT starts
automatically.
• Do not turn off the CKIO output when PLL circuit 1 is in the operating state.
• The CKIO output will be unstable until the PLL circuit stabilizes.
• When a frequency is modified, halt the on-chip DMAC (E-DMAC and DMAC) operation
before the frequency modification.
If PLL circuit 1 or PLL circuit 2 does not become operational after modifying the frequency
modification register (including modification in the operating state), it means that the above
procedure or cautions have not been properly observed. In this case, the WDT will not operate
even though the frequency modification register is modified.
Rev. 2.00, 03/05, page 121 of 884