SH7615 Datasheet, PDF (21/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page Revisions (See Manual for Details)
21.3.3 Bus Timing
805 Conditions amended
Table 21.7 PLL-On Bus
Timing [Modes 0 and 4]
(2)
Conditions: V_CC = PLLV_CC = 3.3 V ± 5%, PV_CC = 5.0 V ±
5%/3.3 V ± 5%, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –5 to +70°C,
SDRAM bus cycle
Figure 21.40 EDO Read 834
Cycle (TRP = 1 Cycle,
RCD = 1 Cycle, No Wait)
Figure 21.40 amended
CAS ⋅
OE
t_OED1
t_OED1
t_OED2
CKE
Rev. 2.00, 03/05, page xxi of xxxviii