SH7615 Datasheet, PDF (314/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.2.8 Refresh Timer Control/Status Register (RTCSR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
RRC2
0
R/W
1
RRC1
0
R/W
0
RRC0
0
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT
and RTCOR match, is set/cleared under the following conditions:
Bit 7: CMF
0
1
Description
[Clearing condition]
After RTCSR is read when CMF is 1, 0 is written in CMF
[Setting condition]
RTCNT = RTCOR
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused
by the CMF bit of RTCSR when CMF is set to 1.
Bit 6: CMIE
0
1
Description
Interrupt request caused by CMF is disabled
Interrupt request caused by CMF is enabled
(Initial value)
Rev. 2.00, 03/05, page 276 of 884