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SH7615 Datasheet, PDF (367/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series | |||
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7.6.3 Basic Timing
The basic timing of a DRAM access is 3 cycles. Figure 7.40 shows the basic DRAM access
timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2
is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access
overlaps the Tc2 cycle of the previous access, so accesses can be performed in a minimum of 3
cycles each.
CKIO
Tp
Tr
Tc1
Tc2
A24âA16
A15âA1
RAS
CASn
RD/WR
Read RD
D31âD0
RD/WR
Write RD
D31âD0
DACKn*
Note: * DACKn waveform when active-low is specified.
Figure 7.40 Basic Access Timing
Rev. 2.00, 03/05, page 329 of 884
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