SH7615 Datasheet, PDF (26/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

3.2.1 Clock Pulse Generator ......................................................................................... 107
3.2.2 Clock Operating Mode Settings........................................................................... 109
3.2.3 Connecting a Crystal Resonator .......................................................................... 112
3.2.4 External Clock Input............................................................................................ 113
3.2.5 Operating Frequency Selection by Register......................................................... 114
3.2.6 Clock Modes and Frequency Ranges................................................................... 122
3.2.7 Notes on Board Design ........................................................................................ 123
3.3 Bus Width of the CS0 Area .............................................................................................. 124
Section 4 Exception Handling ......................................................................................... 125
4.1 Overview........................................................................................................................... 125
4.1.1 Types of Exception Handling and Priority Order ................................................ 125
4.1.2 Exception Handling Operations........................................................................... 127
4.1.3 Exception Vector Table ....................................................................................... 128
4.2 Resets................................................................................................................................ 131
4.2.1 Types of Resets.................................................................................................... 131
4.2.2 Power-On Reset................................................................................................... 131
4.2.3 Manual Reset ....................................................................................................... 132
4.3 Address Errors .................................................................................................................. 132
4.3.1 Sources of Address Errors ................................................................................... 132
4.3.2 Address Error Exception Handling...................................................................... 134
4.4 Interrupts........................................................................................................................... 135
4.4.1 Interrupt Sources.................................................................................................. 135
4.4.2 Interrupt Priority Levels....................................................................................... 136
4.4.3 Interrupt Exception Handling .............................................................................. 136
4.5 Exceptions Triggered by Instructions ............................................................................... 137
4.5.1 Instruction-Triggered Exception Types ............................................................... 137
4.5.2 Trap Instructions.................................................................................................. 137
4.5.3 Illegal Slot Instructions........................................................................................ 138
4.5.4 General Illegal Instructions.................................................................................. 138
4.6 When Exception Sources Are Not Accepted .................................................................... 139
4.6.1 Immediately after a Delayed Branch Instruction ................................................. 139
4.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 139
4.6.3 Instructions in Repeat Loops ............................................................................... 140
4.7 Stack Status after Exception Handling.............................................................................. 141
4.8 Usage Notes ...................................................................................................................... 142
4.8.1 Value of Stack Pointer (SP) ................................................................................. 142
4.8.2 Value of Vector Base Register (VBR)................................................................. 142
4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ........ 142
4.8.4 Manual Reset during Register Access ................................................................. 142
Section 5 Interrupt Controller (INTC)........................................................................... 143
5.1 Overview........................................................................................................................... 143
Rev. 2.00, 03/05, page xxvi of xxxviii