SH7615 Datasheet, PDF (288/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7. If CPU and DMAC bus cycles are set as break conditions when an execution-times break has
been set, BETR will only be decremented once even if CPU and DMAC condition matches
occur simultaneously.
8. UBC and H-UDI are used by the emulator. For this reason, the operation of UBC and H-UDI
may differ in some cases between the emulator and the actual device. If UBC and H-UDI are
not used on the user’s system, no register setting should be performed.
Rev. 2.00, 03/05, page 250 of 884