SH7615 Datasheet, PDF (457/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.1.3 Descriptor Management System
The E-DMAC manages the transmit/receive buffers by means of corresponding transmit/receive
descriptor lists.
Transmission: The transmit E-DMAC fetches a transmit buffer address from the top of the
transmit descriptor list, and transfers the transmit data in the buffer to the transmit FIFO. If a
transmit directive follows in the descriptor, the E-DMAC reads the next descriptor and transfers
the data in the corresponding buffer to the transmit FIFO. In this way, continuous data
transmission can be carried out.
Reception: For each start of a receive DMA transfer, the receive E-DMAC fetches a receive
buffer address from the top of the receive descriptor list. When receive data is stored in the receive
FIFO, the E-DMAC transfers this data to the receive buffer. When reception of one frame is
finished, the E-DMAC performs a receive status write and fetches the receive buffer address from
the next descriptor. By repeating this sequence, consecutive frames can be received.
10.1.4 Register Configuration
The E-DMAC has the seventeen 32-bit registers shown in table 10.1.
Notes: 1. All registers must be accessed as 32-bit units.
2. Reserved bits in a register should only be written with 0.
3. The value read from a reserved bit is not guaranteed.
Rev. 2.00, 03/05, page 419 of 884