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SH7615 Datasheet, PDF (579/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series
Pφ
FRC
N
N+1
OCRA, OCRB
N
Compare match
signal
OCFA, OCFB
Figure 12.11 OCF Setting Timing
12.4.7 Timer Overflow Flag (OVF) Setting Timing
FRC overflow (from H'FFFF to H'0000) sets the timer overflow flag (OVF) to 1. Figure 12.12
shows the timing.
Pφ
FRC
Overflow
signal
H'FFFF
H'0000
OVF
Figure 12.12 OVF Setting Timing
Rev. 2.00, 03/05, page 541 of 884