SH7615 Datasheet, PDF (460/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 0: SWR
Description
0
EtherC and E-DMAC reset is cleared
(Initial value)
1
EtherC and E-DMAC are reset
Notes: 1. If the EtherC and E-DMAC are initialized by means of this register during data
transmission, etc., abnormal data may be sent onto the line.
2. The EtherC and E-DMAC are initialized in 16 internal clocks. Therefore, before
accessing registers in the EtherC and E-DMAC, 16 internal clocks must be waited for.
3. The E-DMAC’s TDLAR, RDLAR, and RMFCRL registers are not initialized. All other
EtherC and E-DMAC registers are initialized.
10.2.2 E-DMAC Transmit Request Register (EDTRR)
The E-DMAC transmit request register issues transmit directives to the E-DMAC.
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 31 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Transmit Request (TR): When 1 is written to this bit, the E-DMAC reads a descriptor, and
in the case of an active descriptor, transfers the data in the transmit buffer to the EtherC.
Bit 0: TR
Description
0
Transmission-halted state. Writing 0 does not stop transmission. Termination of
transmission is controlled by the active bit in the transmit descriptor
1
Start of transmission. The relevant descriptor is read and a frame is sent with
the transmit active bit set to 1
Note:
When transmission of one frame is completed, the next descriptor is read. If the transmit
descriptor active bit in this descriptor has the “active” setting, transmission is continued. If
the transmit descriptor active bit has the “inactive” setting, the TR bit is cleared and
operation of the transmit DMAC is halted.
For details on writing to the register, see section 10.4, Usage Notes.
Rev. 2.00, 03/05, page 422 of 884