SH7615 Datasheet, PDF (179/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

4.7 Stack Status after Exception Handling
The status of the stack after exception handling ends is as shown in table 4.11.
Table 4.11 Stack Status after Exception Handling
Type
Stack Status
Address error
SP → Address of instruction after executed instruction
32 bits
SR
32 bits
Trap instruction
SP → Address of instruction after TRAPA instruction
32 bits
SR
32 bits
General illegal instruction SP → Start address of illegal instruction
32 bits
SR
32 bits
Interrupt
SP → Address of instruction after executed instruction
32 bits
SR
32 bits
Illegal slot instruction
SP → Jump destination address of delayed branch instruction 32 bits
SR
32 bits
Rev. 2.00, 03/05, page 141 of 884