SH7615 Datasheet, PDF (714/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

TIOR0L
Bit 3: Bit 2: Bit 1: Bit 0:
Channel IOC3 IOC2 IOC1 IOC0 Description
0
0
0
0
0
TGR0C is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare
register^*1
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
1
0
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
0
TGR0C is Capture input Input capture at rising edge
1
input
source is TIOCC0 _{Input capture at falling edge}
capture pin
1
*
register^*1
Input capture at both edges
1
*
*
Setting prohibited
*: Don’t care
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00, 03/05, page 676 of 884