SH7615 Datasheet, PDF (431/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.2.10 Collision Detect Counter Register (CDCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC9 COLDC8
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
COLDC7 COLDC6 COLDC5 COLDC4 COLDC3 COLDC2 COLDC1 COLDC0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CDCR is a 16-bit counter that indicates the number of collisions that occurred on the line,
counting from a point 512 bits after the start of data transmission. When the value in this register
reaches H'FFFF (65,535), the count is halted. The counter value is cleared to 0 by a write to this
register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Collision Detect Count 15 to 0 (COLDC15 to COLDC0): These bits indicate the
count of collisions from a point 512 bits after the start of data transmission.
Rev. 2.00, 03/05, page 393 of 884