SH7615 Datasheet, PDF (117/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Instruction
Instruction Code Operation
Cycles
MOV.L @(R0,Rm),Rn
0000nnnnmmmm1110 (R0 + Rm) → Rn
1
MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR)
1
MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR)
1
MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR)
1
MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign
1
extension → R0
MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign 1
extension → R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0
1
MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0
1
MOVT Rn
0000nnnn00101001 T → Rn
1
SWAP.B Rm,Rn
0110nnnnmmmm1000 Rm → Swap the bottom 1
two bytes → Rn
SWAP.W Rm,Rn
0110nnnnmmmm1001 Rm → Swap upper and
1
lower words → Rn
XTRCT Rm,Rn
0010nnnnmmmm1101 Rm: Middle 32 bits of Rn → 1
Rn
T Bit
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Rev. 2.00, 03/05, page 79 of 884