SH7615 Datasheet, PDF (144/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

b. MAC.L @R5+, @R5+ MAC.W and MAC.L can be instruction b. Multiplier access
conflict occurs and execution stall cycle may be produced.
c. LDC R0,SR Changes the saturation arithmetic mode.
Multiplier access conflict occurs between instructions a (DMULU.L) and b (MAC.L), and
execution of instruction b (MAC.L) is stalled. S bit modification (instruction c) is executed
immediately before the MAC.L instruction (b) in the CPU due to the pipeline operation.
Consequently, the sequence of instruction execution b and c is reversed and the MAC.L
operation result becomes an incorrect value.
Countermeasures:
This problem is avoided by any of the following countermeasures.
A. Do not access SR immediately after the multiply-and-accumulate instruction.
B. Insert a NOP instruction before the LDC Rn,SR instruction.
C. Prevent multiplier access conflict (not to produce stall cycles).
Rev. 2.00, 03/05, page 106 of 884